1. Field of the Invention
This invention relates generally to floating gate memory devices such as electrically erasable and programmable read-only memory devices (EEPROMs) and a method for making the same. More specifically, the present invention is directed to the structure and manufacture of an improved single-transistor EEPROM cell suitable for use in high density application.
2. Description of the Prior Art
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROMs provide electrical erasing and a small cell size. FIG. 1 illustrates a prior art cross-sectional view of an asymmetrical flash EEPROM cell 10. The EEPROM cell is formed of a substrate 12, typically of a p-type conductivity, having embedded therein an n.sup.+ drain region 14 and an n-type double-diffused source region 16. The double-diffused source region 16 is formed of a deeply diffused but lightly doped n-junction 18 and a more heavily doped but shallower n.sup.+ junction 20 embedded within the deep n-junction 18. The deeply diffused n-junction 18 is typically formed by using a phosphorous implant, and the shallower n.sup.+ junction 20 is typically formed by using an arsenic implant after the phosphorous implant.
A relatively thin gate dielectric layer 22 (i.e., silicon dioxide having a uniform thickness of about 100 .ANG.) is interposed between the top surface of the substrate 12 and a conductive polysilicon floating gate 24. A polysilicon control gate 26 is insulatively supported above the floating gate 24 by an interpoly dielectric layer 28. The floating gate 24, interpoly dielectric layer 28, and control gate 26 define a stacked gate structure. A channel region 30 in the substrate 12 separates the drain region 14 and the source region 16. The entire structure is overlaid by an oxide insulating layer 32 so as to isolate the transistor cell structure from periphery devices. Further, there are provided means for applying a source voltage V.sub.S through the oxide layer 32 to the source region 16, a gate voltage V.sub.G to the control gate 26, and a drain voltage V.sub.D through the oxide layer 32 to the drain region 14.
According to conventional operation, the flash EEPROM cell of FIG. 1 is "programmed" by applying a relatively high voltage V.sub.G (approximately +12 volts) to the control gate 26 and a moderately high voltage V.sub.D (approximately +9 volts) to the drain 14 in order to produce "hot" (high energy) electrons in the channel 30 near the drain 14. The hot electrons are generated and accelerated across the gate dielectric 22 and onto the floating gate 24 and become trapped in the floating gate since the floating gate is surrounded by insulators. As a result, the floating gate threshold may be increased by 3 to 5 volts. This change in the threshold voltage, or channel conductance, of the cell created by the trapped hot electrons is what causes the cell to be programmed.
In order to erase the flash EEPROM cell of FIG. 1, the relatively high voltage V.sub.S (approximately +12 volts) is applied to the source 16 while the control gate 26 is grounded (V.sub.G =0). The drain 14 is usually allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source region. The electrons trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the n.sup.+ -type source region 16 and are extracted from the floating gate 24 to the source 16 by way of Fowler-Nordheim (F-N) tunneling.
High program and erase voltages for such conventional EEPROM devices are of major concern. Such a requirement has led to a need for a separate high voltage power supply when operating these devices by the provision of a special charge pumping circuit for boosting the power supply voltages to the requisite program and erase levels. The flash EEPROM cell of FIG. 1 suffers from another disadvantage in that the effective channel length L.sub.eff in the p-type substrate will be sensitive to the critical dimensions of the stacked gate structure which is subject to variations and is difficult to precisely control. As a result, the conventional EEPROM cell is incapable of providing scalability to small size (i.e., from 1 micron technology to a sub-half micron design).
It would therefore be desirable to provide an improved single-transistor EEPROM cell structure and a method for making the same so that the effective channel length dimension is independent of the critical dimensions of the stacked gate structure. Further, it would be expedient that the cell structure be able to facilitate scalability to small size and be suitable for use in high density application.